Updating bluetooth bluecore flash using iwrap

This is @jcmvbkbc's suggestion, to implement an exception handler that catches the faulting read and completes it.

Advantages of requiring basically no additional code changes, could potentially work with any/all of .rodata automatically, and is potentially applicable to binary libraries by moving .rodata symbols to irom (symbols that are accessed while SPI flash is unmapped notwithstanding).

updating bluetooth bluecore flash using iwrap-73updating bluetooth bluecore flash using iwrap-37updating bluetooth bluecore flash using iwrap-82

Where the argument is a const at compile time, store it statically in IROM then load it into stack or heap dram at runtime and pass it to the inner wrapped function.

Advantages of being pretty easy to implement (I think), and relatively fast.

This requires changes only to the backend emitter and would be very localised. No need to worry about writes because they are always to dram.

Just need a compiler option (--mforce-l32) and no changes to the source code whatsoever. I get: So around 5% of all loads are l8 or l16 which is pretty low.

So I figured I could at least use some of the awesome features that it's capable of even if they differed from the real one.

Package include: 1 * HM-10 CC2540 4.0 Bluetooth to UART Transceiver Module First off, it's my fault for not knowing my modules before buying. For starters the fake HM-10 still should have a cc2541 chip from Texas Insterments.

l8 on its own would be a good start, as proof of concept.

It might also be enough since I guess that l16 is not used for string processing (except maybe in optimised strcpy/memcpy etc functions which can be de-optimised by hand).

@jcmvbkbc: I guess that's reasonable assumption and compromise, in a sense that other RISC architectures may require natural alignment for accessing sub-word units, and have varying behavior if that doesn't hold (behavior ranging from silently returning undefined data to a fatal fault). And that's pretty different from requiring memory accesses to be on word alignment.

I'm not CPU architectures scholar, and I know only about one more or less popular CPU to have similar restriction - custom XAP core as (was) used in CSR Blue Core Bluetooth So Cs (e.g. That was strictly 16-bit CPU, and not only had no 8-bit operations (like zero/sign extension), but even memory laod/stores were only 16-bit.

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